8. Synchronous-Read Cell🔗

The generated cell reads its memories combinationally: it presents an address and uses the returned word in the same cycle. A technology SRAM macro, like the sky130 macro bound in the synthesis chapter, is synchronous-read: the word is registered and valid one cycle after the address. A cell that binds such macros for every memory must therefore stage each read. This chapter gives that fully synchronous cell an abstract model and proves it commits exactly what the combinational cell does.

The model runs each instruction as three non-overlapped phases. A fetch phase presents the program counter and latches the instruction register. A read phase presents the operand addresses and latches the loaded data word, resident weight, and streamed operand. An execute phase applies the latched instruction and operands. Because the phases never overlap, no architectural state changes between reading an operand and using it, so a latched read equals a live read: the load-use argument is a stability argument, not a hazard argument.

execLatched is the execute-phase transition. It is execDecoded with its three memory reads replaced by latched values: the loaded data word for ld, and the resident weight and streamed operand for kmac. Every other instruction reads only registers and immediates and is unchanged.

One clock advances one phase. Fetch and read leave the architectural state untouched; only execute changes it.

A fetch, a read, and an execute together advance the architectural state by exactly one decoded instruction, the same value the combinational cell produces in one cycle. The synchronous reads change when each result is committed, not what it is.